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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS844252-04 is a 10Gb/12Gb Ethernet Clock Generator and a member of the HiPerClockSTM HiPerClocks TM family of high perfor mance devices from ICS. The ICS844252-04 can synthesize 10 Gigabit Ethernet and 12 Gigabit Ethernet with a 25MHz crystal. It can also generate SATA and 10Gb Fibre Channel reference clock frequencies with the appropriate choice of crystals. The ICS844252-04 has excellent phase jitter performance and is packaged in a small 16-pin TSSOP, making it ideal for use in systems with limited board space.
FEATURES
* Two differential LVDS outputs * Crystal oscillator interface designed for 18pF parallel resonant crystals * Crystal input frequency range: 19.33MHz - 30MHz * Output frequency range: 145MHz - 187.5MHz * VCO frequency range: 580MHz - 750MHz * RMS phase jitter at 156.25MHz (1.875MHz - 20MHz): 0.36ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free compliant packages
IC S
CONFIGURATION TABLE
Crystal Frequency (MHz) 25 25
WITH
25MHZ CRYSTAL
Inputs VCO Frequency (MHz) 750 625 N Output Divide 4 4 Output Frequency (MHz) 187.5 156.25 Application 12 Gigabit Ethernet 10 Gigabit Ethernet
Feedback Divide 30 25
WITH
CONFIGURATION TABLE
Crystal Frequency (MHz) 20 21.25 24 25.5 30
SELECTABLE CRYSTALS
N Output Divide 4 4 4 4 4 Output Frequency (MHz) 150 159.375 150 159.375 187.5 Application SATA 10 Gigabit Fibre Channel SATA 10 Gigabit Fibre Channel 12 Gigabit Ethernet
Inputs Feedback VCO Frequency Divide (MHz) 30 600 30 25 25 25 637.5 600 637.5 750
BLOCK DIAGRAM
OE nPLL_SEL REF_CLK
Pullup Pulldown
PIN ASSIGNMENT
D Q LE nQ1 Q1 VDDO OE nPLL_SEL VDDO Q0 nQ0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT GND REF_CLK CLK_SEL VDD VDDA FREQ_SEL
Pulldown
1
1
XTAL_IN
OSC
XTAL_OUT CLK_SEL
Pulldown
0
Phase Detector
VCO
580MHz-750MHz
DIV. N /4
0
Q0 nQ0 Q1 nQ1
ICS844252-04
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
0 = /25 (default) 1 = /30
FREQ_SEL
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844252AG-04 www.icst.com/products/hiperclocks.html REV. A JANUARY 26, 2006
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 6 4 Name nQ1, Q1 VDDO OE Power Input Type Output Description Differential clock outputs. LVDS interface levels. Output supply pins. Output enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. Pullup LVCMOS/LVTTL interface levels. Selects between the PLL and reference clock as input to the divider. Pulldown When Low, selects PLL. When High, selects reference clock. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Clock select input. When Low, selects cr ystal inputs. When High, Pulldown selects REF_CLK. LVCMOS/LVTTL interface levels. Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
5 7, 8 9 10 11 12 13 14
nPLL_SEL Q0, nQ0 FREQ_SEL VDDA VDD CLK_SEL REF_CLK
Input Output Input Power Power Input Input
GND Power Power supply ground. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT, 15, 16 Input XTAL_OUT is the output. XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 89C/W (0 lfpm)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 70 11 40 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage REF_CLK, CLK_SEL, FREQ_SEL, nPLL_SEL OE REF_CLK, CLK_SEL, FREQ_SEL, nPLL_SEL OE VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
IIH
Input High Current
IIL
Input Low Current
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 400 40 1.25 50 Maximum Units mV mV V mV
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 19.33 Test Conditions Minimum Typical Fundamental 30 50 7 1 MHz pF mW Maximum Units
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT t sk(o) Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz @ Integration Range: 1.875MHz - 20MHz 159.375MHz @ Integration Range: 1.875MHz - 20MHz 187.5MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% Test Conditions Minimum 145 TBD 0.36 0.38 0.38 375 Typical Maximum 187.5 Units MH z ps ps ps ps ps %
t jit(O)
RMS Phase Jitter (Random); NOTE 3
tR / tF
Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots following this section.
844252AG-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
AT
156.25MHZ
Gb Ethernet Filter 156.25MHz
RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.36ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 1k 10k
Phase Noise Result by adding a Gb Ethernet Filter Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
844252AG-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
Noise Power
Qx
3.3V5% POWER SUPPLY + Float GND -
SCOPE
LVDS
nQx
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
RMS PHASE JITTER
nQ0, nQ1 Q0, Q1
t PW
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
VSW I N G Clock Outputs 20% tR tF 20%
DC Input
LVDS
100
VOD/ VOD out
OUTPUT RISE/FALL TIME
VDD out DC Input
DIFFERENTIAL OUTPUT VOLTAGE SETUP
out
VOS/ VOS
OFFSET VOLTAGE SETUP
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LVDS
REV. A JANUARY 26, 2006
80%
80%
out
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844252-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, V DDA, and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F 10
VDDA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844252-04 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
844252AG-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844252AG-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844252-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844252-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 70mA = 242.6mW Power (output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 40mA = 138.6mW Total Power_MAX = 242.6mW + 138.6mW = 381.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.381W * 81.8C/W = 101C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 16-LEADTSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844252-04 is: 2234
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844252-04
FEMTOCLOCKSTM CRYSTAL-TOLVDS CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844252AG-04 ICS844252AG-04T ICS844252AG-04LF ICS844252AG-04LFT Marking 44251A04 44251A04 TBD TBD Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844252AG-04
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